Brain‑inspired computing for space: a review of neuromorphic processors and aerospace opportunities AITranslate
Abstract AITranslate
Conventional processors face fundamental bottlenecks when deployed in resource‑constrained aerospace systems that demand onboard intelligence. This review examines brain‑inspired neuromorphic computing as an alternative, focusing on digital neuromorphic processors with embedded central processing unit (CPU) control, multi‑core architectures, hybrid compute fabrics, and on‑chip learning capabilities for space applications. This review first translates aerospace constraints into chip‑level design requirements, such as low‑power event‑driven computation, sparse communication, hybrid model support, and incremental on‑chip learning. Based on these requirements, we survey four key technical routes in neuromorphic chip designs: heterogeneous control architectures, network‑on‑chip interconnects, hybrid compute fabrics, and on‑chip learning engines. A comparative evaluation of fabricated chips reveals a clear trend toward larger scale, higher energy efficiency, and greater model flexibility. Validation cases across four aerospace domains are examined, though most remain ground‑based with little flight heritage. This review identifies four persistent challenges and outlines corresponding future research lines, including scale, learning, validation and ecosystem aspects. It concludes that neuromorphic chips offer a viable path toward low‑power, adaptive, and robust onboard intelligence, provided that close collaboration bridges the remaining gaps.
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DOI：10.67600/hp.000005
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Citation Information:
Conventional processors face fundamental bottlenecks when deployed in resource‑constrained aerospace systems that demand onboard intelligence. This review examines brain‑inspired neuromorphic computing as an alternative, focusing on digital neuromorphic processors with embedded central processing unit (CPU) control, multi‑core architectures, hybrid compute fabrics, and on‑chip learning capabilities for space applications. This review first translates aerospace constraints into chip‑level design requirements, such as low‑power event‑driven computation, sparse communication, hybrid model support, and incremental on‑chip learning. Based on these requirements, we survey four key technical routes in neuromorphic chip designs: heterogeneous control architectures, network‑on‑chip interconnects, hybrid compute fabrics, and on‑chip learning engines. A comparative evaluation of fabricated chips reveals a clear trend toward larger scale, higher energy efficiency, and greater model flexibility. Validation cases across four aerospace domains are examined, though most remain ground‑based with little flight heritage. This review identifies four persistent challenges and outlines corresponding future research lines, including scale, learning, validation and ecosystem aspects. It concludes that neuromorphic chips offer a viable path toward low‑power, adaptive, and robust onboard intelligence, provided that close collaboration bridges the remaining gaps.
quote
| GB/T 7714-2015 | [1] Yi Zhong, Tao Zhang, Jinhao Ruan, et al. Brain‑inspired computing for space: a review of neuromorphic processors and aerospace opportunities[J]. Hyper, 2026, 1(1): 1-29. DOI:10.67600/hp.000005. |
| MLA | [1] Yi Zhong, et al., "Brain‑inspired computing for space: a review of neuromorphic processors and aerospace opportunities." Hyper, vol. 1, no. 1, 2026, pp. 1-29, https://doi.org/10.67600/hp.000005. |
| APA | [1] Yi Zhong, Tao Zhang, Jinhao Ruan, Yipeng Gao, & Yuan Wang. (2026). Brain‑inspired computing for space: a review of neuromorphic processors and aerospace opportunities. Hyper, 1(1), 1-29. https://doi.org/10.67600/hp.000005 |
| IEEE | [1] Yi Zhong, Tao Zhang, Jinhao Ruan, Yipeng Gao, and Yuan Wang, "Brain‑inspired computing for space: a review of neuromorphic processors and aerospace opportunities," Hyper, vol. 1, no. 1, pp. 1-29, 2026, doi: 10.67600/hp.000005. keywords: {aerospace application;embedded control;hybrid computing;multi-core architecture;neuromorphic chip;on-chip learning} |