3.1.1 Approach 1: pure CPU many‑core

The pure CPU many-core approach uses a large number of programmable processor cores to implement neural computation entirely in software. SpiNNaker [16, 17] is a representative example of this architecture. Instead of relying on dedicated neuron circuits or specialized synaptic accelerators, SpiNNaker maps SNN onto many low-power embedded CPUs. Each SpiNNaker chip integrates 18 ARM cores. Each core can simulate up to about 1000 spiking neurons, while a full-scale SpiNNaker system was designed to scale to over one million cores. This makes the architecture highly scalable and suitable for large-scale real-time SNN simulation.

In this architecture, computation and control are distributed across processor nodes rather than centralized in a host CPU. Each core has local instruction and data tightly coupled memories, as well as peripherals such as a direct memory access (DMA) controller, interrupt controller, timer, and communication controller. Neuron states and frequently used data are stored locally, while larger synaptic data are kept in shared off-chip synchronous dynamic random-access memory (SDRAM) and fetched through DMA when spike events arrive. This organization gives each core a degree of local autonomy in both computation and control.

The main advantage of this approach is flexibility. Since neuron models, synaptic dynamics, and learning rules are implemented in software, the architecture can support different models and network structures without hardware redesign. This makes SpiNNaker suitable for neural model exploration and real-time closed-loop applications.

However, the pure CPU many-core approach also has clear limitations. Neural operations are executed as software instructions on general-purpose cores, so energy efficiency and computational density are lower than in architectures with dedicated neuromorphic accelerators.

3.1.2 Approach 2: instruction‑level collaboration

The second approach introduces instruction-level collaboration between general-purpose processors and neuromorphic computing units. Unlike the pure CPU many-core approach, where all neural operations are executed by programmable CPU cores, this architecture retains dedicated neuromorphic cores for efficient spike-based computation, while using a processor or instruction controller to provide programmability and flexible control. Instead of controlling neuromorphic cores only through coarse-grained configuration commands, this approach allows neural operations, model updates, learning rules, or network-control functions at the instruction level. Darwin3 [18] and the Fullerene-like heterogeneous neuromorphic system-on-chip (SoC) [19] are representative examples of this design direction.

Darwin3 and the Fullerene-like neuromorphic SoC both adopt an instruction-level collaborative architecture that couples programmable control with dedicated neuromorphic computation. Darwin3 organizes its computing nodes in a 24×24 mesh, with neuron cores connected by an on-chip network and a RISC-V node for chip management. It introduces a domain-specific neuromorphic instruction set architecture (ISA) to control state loading, neuron/synapse updates, weight updates, and spike generation, enabling different models and learning rules on shared hardware datapaths. Similarly, the Fullerene-like SoC integrates a RISC-V CPU with 20 neuromorphic cores, where an Extended Neuromorphic Unit decodes dedicated instructions for network initialization, core enabling, and execution control, and sends control signals to the neuromorphic processor through a neuromorphic bus. In both cases, RISC-V-based instruction control improves programmability, while specialized neuromorphic cores retain efficient spike processing.

From the control-architecture perspective, this approach provides a middle ground between fully software-based many-core systems and coarse-grained host-controlled computing cores. Compared with pure CPU many-core architectures, dedicated neuromorphic cores offer higher energy efficiency and better spike-processing density. Compared with traditional host CPU plus computing core designs, instruction-level extensions provide more fine-grained and flexible control over neuromorphic operations.

However, the flexibility of this approach is still constrained by the supported instruction set and hardware datapath. Darwin3 can support various neuron models and learning rules through its domain-specific ISA, while the Fullerene-like SoC supports efficient heterogeneous control through RISC-V extensions. Nevertheless, arbitrary computation remains less flexible than in a fully programmable CPU many-core system. In addition, because neural operations must match predefined instruction formats or specialized datapaths, computing performance may be limited when models deviate from the supported operation patterns.

3.1.3 Approach 3: host CPU + accelerator array

The third approach adopts an architecture with a host CPU and neuromorphic accelerator arrays. In this design, general-purpose processors are mainly responsible for coarse-grained system management, configuration, task scheduling, and communication control, while large arrays of neuromorphic cores execute spike-based neural computation. Loihi [20] and PAICORE are representative examples of this architecture.

Loihi integrates 128 neuromorphic cores, 3 embedded x86 cores, and off-chip interfaces on a many-core mesh, with packetized messages used for core configuration, execution control, spike communication, and synchronization. PAICORE series adopts a similar hierarchy with one RISC-V CPU, 63 offline cores, and 17 online cores; the RISC-V core manages instruction parsing, task scheduling, routing control, and learning configuration, while the core array performs parallel SNN/ANN computation. In both cases, the CPU does not directly execute most neural operations but configures and coordinates the accelerator array through message passing, resulting in relatively low CPU intervention during neural execution.

This architecture reduces the control burden on the host processor. Once the network is configured, neuromorphic cores can independently process spikes, update neuron states, access local synaptic memory, and exchange spike messages through the NoC. Therefore, compared with pure CPU many-core systems, the CPU overhead is lighter and the neural computation efficiency is higher.

However, this approach is generally less flexible than pure CPU or instruction-level collaborative architectures. The CPU interacts with the accelerator array mostly at a coarse granularity, while the internal behavior of neuromorphic cores is constrained by predefined neuron models, synaptic formats, routing mechanisms, and learning modules. Although Loihi supports programmable learning rules and PAICORE series supports multiple task modes and RISC-V functional extensions, their control model is still primarily based on configuring and managing accelerator cores rather than freely programming each neural operation.

Overall, the three heterogeneous control architectures reflect different trade-offs among flexibility, performance, and control overhead. The pure CPU many-core approach, represented by SpiNNaker, offers the highest programmability because neuron models, synaptic dynamics, and control logic are implemented in software. However, this flexibility comes with relatively low computational density and energy efficiency, since neural operations are executed as general-purpose instructions. The instruction-level collaborative approach, represented by Darwin3 and the Fullerene-like neuromorphic SoC, introduces custom neuromorphic instructions and RISC-V-based control to balance programmability and hardware efficiency. It provides better performance than pure CPU execution while preserving moderate model flexibility. The host CPU with accelerator array approach, represented by Loihi and PAICORE series, achieves higher execution efficiency and lower CPU control burden by offloading neural computation to dedicated cores, but its flexibility is more constrained by predefined accelerator datapaths, routing mechanisms, and supported neural primitives.

For aerospace applications, embedded CPU/RISC-V integration is valuable because it enables local autonomous control close to neuromorphic resources. In airborne and spaceborne systems, relying on a distant central processor may introduce latency, increase communication energy, and reduce robustness. By placing an embedded controller on chip or within the neuromorphic module, functions such as network initialization, parameter updates, event scheduling, runtime monitoring, fault detection, and adaptive reconfiguration can be performed locally. This supports real-time perception, navigation, target tracking, and closed-loop control under strict latency and power constraints. It also improves system resilience: when communication with a host processor or ground station is delayed, interrupted, or bandwidth-limited, the local controller can continue managing neural execution and maintain partial functionality through distributed control.

Embedded CPU/RISC-V integration also supports software ecosystem reuse and domain-specific extensibility. Compared with purely custom control logic, CPU/RISC-V-based architectures can reuse mature compilers, toolchains, debugging interfaces, runtime libraries, and embedded software development practices. This reduces the engineering cost of deploying neuromorphic chips in aerospace systems and facilitates integration with existing avionics or spacecraft computing platforms. At the same time, RISC-V allows custom instruction extensions or tightly coupled control units for spike routing, network configuration, learning control, and event management. Therefore, aerospace neuromorphic processors can combine efficient event-driven neural cores with programmable local control, software portability, and application-specific customization.

Specifically, Figure 3 compares the three heterogeneous control architectures, i.e., pure CPU many‑core, instruction‑level collaboration, and host CPU with accelerator array, highlighting their trade‑offs in flexibility and efficiency.

Figure 3 Heterogeneous control architectures in neuromorphic chips.

From the perspective of aerospace workloads, the preferred control architecture depends strongly on the required degree of autonomy and runtime flexibility. For closed-loop navigation and control, the key requirement is not only high throughput but also bounded and deterministic latency from sensor input to control output. Therefore, architectures with tightly coupled embedded CPU/RISC-V controllers and neuromorphic accelerator arrays are attractive because they can perform local scheduling, health monitoring, emergency response, and runtime reconfiguration without relying on a remote host processor or ground station. This is important for obstacle avoidance, docking assistance, attitude-related perception, target tracking, and other safety-critical perception-control loops.

By contrast, more programmable CPU many-core or instruction-level collaborative architectures are useful when the mission requires runtime model modification, algorithm exploration, or flexible adaptation to changing sensor workloads. For example, scientific payloads, exploratory probes, or experimental onboard AI platforms may benefit from software-defined neuron models, programmable learning rules, and instruction-level control over neural operations. Therefore, aerospace neuromorphic processors may adopt different control styles according to mission risk, latency requirement, and model flexibility: accelerator-array control is suitable for efficient and deterministic execution, while instruction-level or CPU many-core control provides stronger programmability for adaptive and exploratory workloads.

3.2.1 Aspect 1: topology architecture

The topology architecture of the NoC determines the basic communication paths among neuromorphic cores and strongly affects latency, bandwidth, scalability, and hardware complexity.

2D mesh is one of the most commonly used NoC structures, as seen in TrueNorth [21, 22], Tianjic [15], Darwin3 [18], and PAICORE 1.0 [23]. It arranges cores in a regular grid and connects each router to its neighboring routers. This topology is simple, modular, and layout-friendly, making it suitable for planar chip implementation. However, as the chip scale increases, the average hop count becomes larger, leading to higher latency and energy consumption for long-distance communication.

Tree and fat-tree topologies, adopted in systems such as DYNAPs [24] and PAICORE 2.0 [25], organize routers hierarchically. They can reduce communication distance by aggregating and distributing traffic through upper-level routers, thus providing relatively low latency for many traffic patterns. However, traffic may concentrate near the root or high-level routers, causing potential congestion. Fat-tree designs alleviate this issue by increasing upper-level bandwidth, but at the cost of higher wiring and area overhead.

Mixed, star, and butterfly-like topologies, used in systems such as Loihi [20], SpiNNaker [16, 17], and 10-nm FinFET [26] neuromorphic chips, introduce more flexible global connections. These structures can reduce long-distance communication latency and improve bandwidth utilization for irregular neural traffic. Nevertheless, they usually require more complex router designs, routing control, and physical implementation compared with regular mesh or tree structures.

3D topologies, represented by Duallearn [27], extend the interconnect from the 2D plane to the vertical dimension. By exploiting die stacking or 3D integration, they can shorten communication paths, improve scalability, and naturally support multi-layer or multi-chip neuromorphic systems. This structure is particularly promising for workloads with 3D data reuse and dense multicast communication.

Hexagonal topologies have recently emerged as a balanced alternative for neuromorphic NoCs. NeuroHexa [28] proposes a honeycomb-structured hexagon topology where each router connects to six neighbors, supporting both 2D planar expansion and 3D vertical stacking through chiplet integration. The architecture also incorporates GALS group thread control and configurable routing modes to adapt to diverse traffic patterns.

Overall, topology architecture reflects a trade-off between simplicity, latency, bandwidth, scalability, and implementation complexity. While 2D mesh remains attractive for its regularity, hierarchical and mixed topologies improve communication efficiency, and 3D hexagonal NoC provides a promising direction for highly scalable neuromorphic processors.

3.2.2 Aspect 2: routing algorithm

The routing algorithm determines how packets are forwarded through the NoC from source cores to destination cores. It directly influences communication latency, congestion behavior, hardware cost, and deadlock freedom. In neuromorphic NoCs, routing algorithms are commonly designed to support massive spike/event transmission with low overhead.

Dimensional routing is a widely used deterministic routing strategy. A typical example is X-Y dimension-ordered routing, where packets are first routed along the X dimension and then along the Y dimension until they reach the destination. This method is simple, predictable, and easy to implement in hardware. More importantly, because packets follow a fixed dimension order, cyclic channel dependencies can be avoided, making the routing naturally deadlock-free. However, dimensional routing lacks flexibility. When certain links or regions become congested, packets cannot dynamically choose alternative paths, which may lead to local traffic hotspots and increased latency.

Adaptive routing improves routing flexibility by selecting paths according to real-time network conditions. In congestion-aware self-adaptive routing, routers monitor link availability, buffer occupancy, or local traffic pressure, and then choose a less congested path for packet forwarding. This mechanism can better balance network load and reduce packet latency under irregular or bursty spike traffic. It is particularly useful for large-scale neuromorphic systems, where communication patterns are often sparse, dynamic, and difficult to predict. However, adaptive routing introduces higher hardware and control complexity. It must also be carefully designed to ensure deadlock freedom, since unrestricted path selection may create cyclic dependencies among channels.

3.2.3 Aspect 3: multicast mechanism

The multicast mechanism is critical in neuromorphic NoCs because a single spike event often needs to be delivered to multiple postsynaptic cores. Efficient multicast can reduce redundant packet transmission, improve bandwidth utilization, and lower communication energy.

Lookup-table-based routing is adopted in systems such as Tianjic [15] and SpiNNaker [16, 17]. In this mechanism, routing information is stored in local tables, and each incoming spike packet is matched against the table to determine its destination cores or output links. When multiple targets are required, the router or target core can generate several packet copies according to the stored entries. This approach is flexible and supports programmable neural connectivity. However, it requires additional memory resources for routing tables, and packet replication may increase traffic load if many copies are generated near the source or at the destination core.

Packet-analysis-based routing is used in systems such as DYNAPs [24] and PAICORE series [23, 25]. Instead of relying only on large lookup tables, routers analyze packet fields step by step during transmission and decide whether forwarding or multicast replication is needed along the routing path. In this way, packets can be duplicated at intermediate routers only when their paths diverge, reducing unnecessary long-distance repeated transmissions. This mechanism can improve bandwidth efficiency and is more suitable for structured multicast patterns in large-scale NoCs. However, it may require more complex router logic and careful packet format design.

Overall, lookup-table routing offers high flexibility and programmability but may introduce memory overhead and redundant packet copies. Packet-analysis routing can reduce duplicated traffic by performing multicast along the routing path, but it increases routing logic complexity. For neuromorphic processors, an efficient multicast mechanism is essential for supporting massive fan-out spike communication with low latency and low energy consumption.

For aerospace applications, neuromorphic processors are expected to provide real-time perception, autonomous decision-making, and onboard intelligent processing under strict constraints on power, area, weight, and reliability. In this context, efficient NoC interconnects are especially important because communication often becomes a major source of latency and energy consumption in large-scale neural workloads. The integration of 3D topology and efficient multicast mechanisms provides a promising solution for satellite and spaceborne neuromorphic systems. A 3D NoC can shorten communication paths by exploiting vertical interconnects between stacked dies, thereby reducing the average hop count and transmission latency. At the same time, multicast support allows a single spike or feature event to be efficiently delivered to multiple destination cores without generating excessive redundant packets. When multicast replication is performed along the routing path, communication bandwidth can be better utilized and unnecessary packet movement can be reduced.

These advantages are particularly valuable for satellites, where energy supply and thermal dissipation are limited. Lower communication latency enables faster response in time-sensitive tasks such as remote sensing, object detection, navigation, and anomaly monitoring. Reduced data movement also lowers power consumption, which helps extend mission lifetime and improve system robustness. Therefore, 3D multicast-integrated NoC architectures are well suited for compact, energy-efficient, and scalable neuromorphic processors in aerospace platforms.

Accordingly, Figure 4 illustrates the key NoC design aspects for neuromorphic systems, including topology architectures, routing algorithms, and multicast mechanisms.

Figure 4 Network-on-chip interconnects: topologies, routing, and multicast. Some elements of this graphic (the icons) were created using GPT-5.6 (OpenAI). For image credits, please see the Disclosing the use of AIGC section of this article.

The preferred NoC design also depends on the aerospace workload. Visual target detection, tracking, and pose estimation may generate bursty feature or spike traffic across multiple processing cores, especially when event-based sensors and frame-based convolutional neural network (CNN) backbones are jointly used. Such workloads benefit from multicast-aware routing and efficient packet replication, because feature events or spike packets may need to be delivered to multiple downstream cores. Always-on anomaly monitoring, in contrast, usually has a low average event rate and requires extremely low idle communication overhead. In this case, the NoC should minimize unnecessary packet movement and keep inactive links or routers in low-power states.

Closed-loop navigation and control place different requirements on the interconnect. For these tasks, predictable communication latency and bounded worst-case response time are often more important than average throughput. Deterministic or carefully constrained adaptive routing can therefore be useful for safety-critical control loops. Long-duration spacecraft operation further requires fault-aware routing and graceful degradation, because radiation-induced faults or aging effects may affect routers, links, or buffers during the mission. In this sense, aerospace-oriented NoC design should consider not only topology scalability and multicast efficiency, but also workload-dependent latency predictability, idle power, and fault tolerance.

3.3.1 Fabric 1: SNN-only design

SNN-only fabrics are neuromorphic processors dedicated to SNN execution. Their main feature is the direct hardware implementation of spike-based computation and neuronal dynamics, typically based on the leaky integrate-and-fire (LIF) model. Instead of performing dense high-precision multiply-accumulate (MAC) operations as in ANN accelerators, these chips process discrete spike events and update neuron states only when necessary, enabling highly sparse and energy-efficient computation.

Representative examples include TrueNorth [21, 22] and Loihi [20]. TrueNorth is one of the earliest large-scale digital neuromorphic processors. It integrates a large number of neurosynaptic cores, where each core contains programmable neurons, synapses, and routing logic. The architecture is designed around massively parallel spike communication and lightweight neuronal updates. Instead of supporting conventional high-precision arithmetic, TrueNorth focuses on low-bit synaptic operations and simple neuron state evolution. This makes it highly energy-efficient for tasks such as pattern recognition, event-based vision, and sensory classification, but less flexible for workloads requiring precise numerical computation or complex deep learning layers. Intel Loihi further extends the SNN-only design philosophy by introducing more programmable neuron models and on-chip learning support. Loihi cores implement LIF-based neuronal dynamics, spike routing, synaptic state updates, and local learning rules.

The main advantage of SNN-only fabrics lies in their high energy efficiency for sparse, event-driven computation. Since neurons update primarily when spikes arrive, unnecessary switching activity is reduced. This property is well matched to event-based sensors, such as dynamic vision sensors, auditory sensors, and other asynchronous sensing front ends. However, because they are specialized for spike-based operations, they have limited support for conventional ANN layers or high-precision computation. Therefore, SNN-only fabrics are suitable for low-power neuromorphic sensing, but less effective for applications requiring both SNN and ANN workloads on the same hardware.

3.3.2 Fabric 2: SNN-ANN design

SNN-ANN fabrics aim to support both conventional ANN and SNN on the same hardware platform. This design addresses the limitation of SNN-only processors, which are highly efficient for event-driven workloads but lack efficient support for dense high-precision ANN computation.

Representative examples include C-DNN [29], Tianjic [15], and PAICORE 2.0 [25]. These architectures usually adopt one of two design strategies. The first strategy is to integrate separate ANN and SNN cores on the same chip, allowing each core type to be optimized for its own computation pattern. ANN cores focus on dense matrix or convolution operations, while SNN cores handle spike routing, membrane potential updates, and firing events. The second strategy is to design a reconfigurable computing unit, where the same arithmetic logic can switch between ANN and SNN modes. For example, the arithmetic logic unit‌ (ALU) may perform multiply-accumulate operations for ANN layers, or accumulate incoming spikes and compare membrane potentials with thresholds for SNN layers.

The main advantage of SNN-ANN fabrics is improved flexibility. They can execute hybrid models in which SNN layers are used for low-power sensory processing, while ANN layers provide higher-accuracy feature extraction, classification, or decision making. This makes them more suitable than SNN-only chips for applications that require both energy efficiency and computational accuracy.

However, SNN-ANN fabrics also introduce higher design complexity. The hardware must support different data representations, computation schedules, and memory access patterns. ANN workloads usually require dense and regular computation, whereas SNN workloads are sparse, asynchronous, and event-driven. Efficiently sharing memory, routing resources, and processing units between these two modes is therefore a key architectural challenge.

3.3.3 Fabric 3: spike-Transformer design

Spike-Transformer fabrics are emerging architectures designed to support Transformer-based models implemented with spiking computation. Compared with SNN-only and SNN-ANN fabrics, this type of design targets more complex workloads, such as vision Transformers and large language model inference, while attempting to retain the energy benefits of spike-based processing. A representative example is C-Transformer [30], which supports spiking-converted Transformer models. In such architectures, key Transformer operations, including linear projection, attention-related computation, and feed-forward layers, are adapted to spike-based or event-driven execution. Instead of continuously processing dense high-precision activations, spike-Transformer fabrics exploit sparse spike activity to reduce unnecessary computation and data movement.

The main feature of this fabric is its ability to bridge SNN and Transformer models. It allows Transformer layers to be mapped onto neuromorphic-style hardware through spike encoding, temporal accumulation, and event-driven processing. This makes it possible to execute converted large language model (LLM) or Transformer models with lower power consumption than conventional dense accelerators, especially when activation sparsity can be effectively exploited.

However, spike-Transformer fabrics are more complex than SNN-only or basic SNN-ANN designs. Transformer models involve attention mechanisms, large matrix operations, and significant memory traffic, which are difficult to fully convert into efficient spike-based computation. Maintaining model accuracy after spike conversion is also a major challenge, particularly for large-scale language tasks.

Hybrid compute fabrics are particularly valuable for aerospace systems because they can integrate low-power sensing and high-accuracy decision making on the same chip. In aerospace platforms, such as satellites, spacecraft, unmanned aerial vehicles, and deep-space probes, computing resources are strongly constrained by power, size, weight, and thermal limits. A unified SNN-ANN or spike-Transformer fabric can reduce the need for separate processors and improve system-level efficiency.

In such a system, SNN layers can be used as an always-on sensing front end. They are well suited for processing sparse and event-driven signals from vision sensors, infrared detectors, auditory sensors, or other environmental monitoring devices. Since SNN computation is activated mainly by spike events, it can significantly reduce energy consumption during continuous perception. Meanwhile, ANN layers or Transformer layers can be used for high-accuracy inference and decision making. When complex recognition, target tracking, navigation, fault diagnosis, or mission planning is required, the system can activate ANN or spike-Transformer modules to provide stronger representation and reasoning capability. This allows the platform to balance energy efficiency and task accuracy according to mission requirements.

Therefore, mixed SNN-ANN and spike-Transformer models offer a promising computing approach for aerospace edge intelligence. They enable compact, adaptive, and energy-efficient onboard AI systems that can perform continuous sensing, intelligent analysis, and autonomous decision making without relying heavily on ground communication or large-scale computing resources.

As illustrated, Figure 5 shows the evolution of hybrid compute fabrics from SNN‑only to SNN‑ANN and spike‑Transformer designs.

Figure 5 Hybrid compute fabrics: from SNN-only to SNN-ANN and spike-Transformer. Some elements of this graphic (the icons) were created using GPT-5.6 (OpenAI). For image credits, please see the Disclosing the use of AIGC section of this article.

More explicitly, different aerospace scenarios require different model structures and compute fabrics. Table 2 summarizes the relationship between representative aerospace workloads, model requirements, suitable neuromorphic fabrics, and architectural implications. This mapping shows that SNN-only, SNN-ANN, and spike-Transformer fabrics should be regarded as complementary design choices rather than as a single evolutionary path. For always-on monitoring, an SNN-only or SNN-front-end design can minimize idle power because computation is activated mainly by sparse events. For visual target detection, tracking, and pose estimation, however, dense convolutional or YOLO-like CNN detectors are often required to achieve high localization accuracy, making SNN/CNN-compatible acceleration more suitable. Event-camera navigation and high-speed tracking may require a hybrid event-frame pipeline, where sparse event-driven processing is combined with ANN/CNN feature extraction. Closed-loop navigation and control additionally require deterministic scheduling and local runtime control, while multimodal fusion and autonomous planning require flexible dataflow and heterogeneous compute resources. Therefore, the architectural choice should be driven by the sensing modality, task accuracy, latency constraint, and energy budget of each aerospace scenario.

3.4.1 Design 1: biomimetic‌ learning rule

A common design for on-chip learning engines is to employ biomimetic learning rules, such as Hebbian learning, Spike-Timing-Dependent Plasticity (STDP), and Spike-Driven Synaptic Plasticity (SDSP). These rules update synaptic weights according to local neural activities, including pre-synaptic and post-synaptic spike correlations or their relative timing. Since the required information is locally available at the synapse, they are well suited to neuromorphic hardware implementation.

The major advantage of biomimetic learning rules is their low hardware cost. They do not require global error backpropagation, gradient storage, or complex optimization procedures. Instead, synaptic updates can be triggered by spike events, which matches the sparse and event-driven nature of spiking neural networks. Therefore, these methods are attractive for low-power online adaptation and have been adopted in neuromorphic systems such as ROLLS [31], ODIN [32], MorphIC [33], PAICORE 2.0 [25], and temporal STDP [34]. These platforms demonstrate that biomimetic learning rules can be efficiently embedded into neuromorphic architectures and can provide a practical path toward online adaptation without relying on external training infrastructure.

However, these rules are mostly unsupervised or weakly supervised, and their learning capability is limited. Because weight updates rely mainly on local information, they suffer from poor global credit assignment, especially in multilayer or deep networks. As a result, biomimetic learning rules are effective for simple feature extraction, clustering, or adaptive behaviors, but usually achieve lower accuracy on complex task-driven learning compared with supervised training methods.

Therefore, this design is most suitable for lightweight online adaptation, unsupervised representation learning, and low-power autonomous systems, but it is generally insufficient as a standalone solution for training complex deep spiking neural networks.

3.4.2 Design 2: backpropagated learning rule

Another important design for on-chip learning engines is to support backpropagated learning rules, such as Backpropagation through Time (BPTT) and surrogate-gradient-based methods including Spatio-Temporal Backpropagation (STBP). Unlike biomimetic rules that rely only on local spike correlations, these methods introduce task-level error signals to guide synaptic updates. Therefore, they can optimize spiking neural networks toward specific objectives and are more suitable for supervised learning tasks.

The main advantage of backpropagated learning is its high accuracy and broad applicability. By propagating error information across layers and time steps, BPTT and STBP can address the credit assignment problem in deep ANN and SNN. This makes them effective for complex perception and decision-making tasks, where purely local learning rules often fail to achieve sufficient performance. Recent neuromorphic platforms such as H2Learn [35] and DualLearn [27] have explored or supported such supervised on-chip learning mechanisms, demonstrating their potential for more capable adaptive intelligence.

However, this design also introduces significant hardware overhead. Backpropagated learning requires storing intermediate neuronal states, spike activities, membrane potentials, and temporal information for gradient computation. In addition, error propagation and weight updates involve more complex arithmetic and memory access than local plasticity rules. These requirements increase chip area, energy consumption, and design complexity, especially for large-scale networks or long temporal sequences.

3.4.3 Design 3: forward learning rule

A third design direction is to employ forward learning rules, such as e-prop, Sparse Target Propagation (S-TP), and zero-order perturbation-based learning. Unlike conventional backpropagation-based methods, forward learning avoids explicit backward error propagation through the network. Instead, synaptic updates are computed during or immediately after the forward dynamics, using locally maintained variables, eligibility traces, feedback signals, or perturbation-based estimates.

The key advantage of forward learning is its balance between learning capability and hardware efficiency. Compared with biomimetic rules, forward learning can incorporate task-related signals and thus provide better adaptation for incremental or supervised scenarios. Compared with BPTT or surrogate-gradient backpropagation, it reduces the need to store full temporal trajectories and avoids complex backward computation, making it more suitable for online and resource-constrained hardware implementation. For example, e-prop uses eligibility traces to approximate temporal credit assignment in recurrent spiking neural networks, enabling online learning with reduced memory requirements. S-TP introduces synaptic-level plasticity triggered by forward activity and task feedback, while zero-order perturbation methods estimate learning directions by observing output changes under small parameter or activity perturbations. Neuromorphic chips such as ReckOn [11] and ANP-I [36] demonstrate the potential of these approaches for on-chip adaptation and incremental learning.

However, forward learning rules also have limitations. Their performance is often dependent on specific network structures, feedback designs, or perturbation mechanisms. Compared with full backpropagation, they may provide less accurate gradient information, which can limit convergence speed and final task accuracy. In addition, some methods are effective only for certain models or learning scenarios, making their general applicability weaker than standard backpropagation-based training.

For aerospace applications, on-chip learning engines are particularly valuable because they enable on-orbit incremental learning without continuous ground intervention. Spacecraft, satellites, and planetary probes often operate in dynamic and uncertain environments, where communication with ground stations is delayed, intermittent, or bandwidth-limited. In such cases, relying solely on pre-trained models may be insufficient when the onboard system encounters new conditions, unexpected targets, sensor degradation, or distribution shifts.

With on-chip learning capability, aerospace platforms can adapt their models directly during operation. In sample-incremental learning, the system updates its parameters using newly observed samples, allowing it to improve performance under changing illumination, background, noise, or orbital conditions. In this way, the system can further recognize and incorporate new object categories or event types that were not included in the original training set, such as unknown space debris, abnormal equipment states, or novel surface features during planetary exploration. This capability reduces dependence on frequent data downlink, ground-based retraining, and model re-uploading. It also improves mission autonomy, responsiveness, and robustness, which are critical for long-duration or deep-space missions. Therefore, on-chip learning engines provide an important hardware foundation for adaptive onboard intelligence, enabling spacecraft to continuously learn from local data and maintain reliable performance in changing aerospace environments.

Finally, Figure 6 categorizes on‑chip learning engines into biomimetic rules, backpropagated learning, and forward learning schemes, illustrating their respective advantages and hardware costs.

Figure 6 On‑chip learning engines: biomimetic, backpropagated, and forward learning rules. Some elements of this graphic (the icons) were created using GPT-5.6 (OpenAI). For image credits, please see the Disclosing the use of AIGC section of this article.

The choice of on-chip learning mechanism should also be matched to the risk level, supervision availability, and adaptation objective of each aerospace scenario. Although biomimetic local learning, backpropagated learning, and forward learning provide different trade-offs between learning capability and hardware cost, their practical value becomes clearer when they are connected to specific onboard use cases. Table 3 summarizes this relationship.

Therefore, on-chip learning in aerospace systems should be mission- and risk-dependent. Lightweight biomimetic local learning is suitable for low-risk adaptation tasks where low memory and energy overhead are more important than global optimization accuracy, such as sensor recalibration, anomaly threshold adjustment, and compensation for gradual sensor drift. Supervised local-error, prototype-based, or forward-learning mechanisms are more suitable for few-shot class insertion and task-oriented perception adaptation, where the system needs to incorporate new object categories, event types, or environmental patterns from a small number of samples. More complex BP/BPTT/STBP-like learning can provide stronger optimization capability and higher task accuracy, but its storage, computation, and energy overhead make it difficult to deploy as a general-purpose in-orbit learning mechanism. In practice, such learning may be limited to small subnetworks, infrequent update windows, non-critical mission phases, or scenarios where ground supervision and safety checks are available. This suggests that future space-oriented neuromorphic chips should support hierarchical and bounded learning modes rather than a single unrestricted online training mechanism.

4.1.1 Integration scale: from small learning cores to Million-Neuron systems

From the perspective of integration scale, fabricated neuromorphic chips have evolved from small learning cores to hundred-thousand-neuron systems and, more recently, to million-neuron digital many-core platforms. Early chips primarily focused on demonstrating the feasibility of neuromorphic computing, including local plasticity, event-driven communication, analog neural dynamics, and multi-chip scalability. With advances in process technology, on-chip memory, and interconnect capability, neuromorphic processors have gradually moved beyond prototype validation toward system-level platforms capable of supporting complex SNN workloads and multi-task edge-intelligence applications.

SpiNNaker [16, 17], Neurogrid [37], and BrainScaleS [38, 39] represent three distinct routes among early large-scale neural simulation systems. SpiNNaker uses an array of general-purpose processor cores to realize real-time neural simulation and emphasizes system expansion through multi-chip interconnection. Neurogrid adopts an analog/mixed-signal approach to emulate large-scale neural dynamics at low power. BrainScaleS demonstrates another highly parallel neuromorphic route through wafer-scale integration and accelerated neural-dynamics emulation. Compared with these platforms, which are mainly oriented toward neural simulation, TrueNorth [21, 22], Loihi [20], Darwin [40], Tianjic [15], and the PAICORE series [23, 25] highlight a stronger trend toward digitalization, many-core organization, and programmability, pushing neuromorphic chips into the stage of million-neuron integration and large-scale synaptic mapping.

TrueNorth, for example, integrates one million neurons and 256 million synapses in a 28 nm process, making it a representative early million-scale digital SNN chip. The Loihi series further expands this direction by emphasizing programmable neurons, on-chip learning, and asynchronous event-driven communication. The Darwin series has evolved from an early 32k-neuron platform to Darwin3 [18] at the million-neuron scale, reflecting the progress of domestic digital neuromorphic platforms. Tianjic [15] and TianjicX [41] increase neuron scale while introducing hybrid ANN/SNN computation. PAICORE series [23, 25] further improve neuron capacity, synaptic capacity, and on-chip static random-access memory (SRAM), making them representative platforms with strong large-scale SNN mapping capability and high-density local storage.

For aerospace edge intelligence, integration scale is important not only because it determines how many neurons and synapses can be mapped onto the chip, but also because it affects whether complex tasks can be completed in a closed loop on board. Spaceborne vision, space-object recognition, attitude perception, fault diagnosis, and autonomous obstacle avoidance often require the simultaneous processing of temporal signals, sparse events, and multimodal sensory information. Larger neuron arrays, higher synaptic capacity, and more sufficient on-chip storage can reduce off-chip memory accesses and dependence on ground communication, thereby lowering system power, shortening response latency, and improving in-orbit autonomous processing capability.

4.1.2 Throughput and energy efficiency: from low-power SNN inference to heterogeneous high-throughput computing

Throughput and energy efficiency are central metrics for evaluating neuromorphic chips. In aerospace scenarios, however, they should not be interpreted independently of task workload, power budget, and thermal-design constraints. Unlike conventional AI accelerators that emphasize dense matrix-multiplication throughput, the advantage of neuromorphic chips mainly arises from event-driven operation, sparse activation, local storage, and low communication overhead. Therefore, reported metrics such as tera synaptic operations per second (TSOPS), giga spikes per second (Gspike/s), or giga synaptic operations per second per watt (GSOPS/W) must be understood together with the supported models, spike sparsity, data precision, learning modes, and application contexts.

A clear development trend can be observed. Early representative digital neuromorphic chips first demonstrated the feasibility of large-scale low-power SNN inference. TrueNorth showed the potential of a million-neuron digital SNN inference platform with a peak synaptic operation capability of 58 GSOPS. Loihi further expanded the capability boundary of SNN chips by introducing programmable neuromorphic computation and on-chip learning. Later, compact chips oriented toward specific tasks and low-power online learning emerged. For example, the ReckOn [11] and ANP series [36, 42, 43, 44, 45] achieved high synaptic operation (SOP) energy efficiency within small silicon areas, indicating that dedicated neuromorphic architectures can provide clear energy-efficiency advantages in temporal processing, online learning, and incremental learning.

In recent years, the throughput and energy-efficiency trajectory of neuromorphic chips have extended from pure SNN inference to high-throughput heterogeneous computing. Tianjic [15] expands neuromorphic computation to hybrid ANN/SNN processing, while TianjicX [41] further raises performance to the tera operations per second (TOPS) level and energy efficiency to the TSOPS/W level. PAICORE 2.0 [25] reaches 20.74 TSOPS and 5.181 TSOPS/W in SNN mode and also provides high throughput and energy efficiency in ANN 1-bit mode. DualLearn [27] targets heterogeneous training and inference by supporting richer computation across SNN inference, ANN inference, and learning modes. C-DNN [29] and C-Transformer [30] further show that neuromorphic computing is not limited to traditional SNNs; it can also be combined with CNNs, Transformers, and spiking Transformers to form efficient platforms for complex perception and sequence-modeling tasks.

This trend is directly relevant to aerospace applications. Onboard intelligent systems require always-on low-power perception, but they also need to execute high-accuracy recognition, target tracking, path planning, and autonomous decision-making at critical moments. Therefore, the value of future neuromorphic chips will not lie only in ultra-low-power SNN inference. It will also depend on whether the same platform can dynamically switch across different computation densities, model types, and task phases. In other words, neuromorphic processors for aerospace edge intelligence should combine low standby power, high instantaneous throughput, and controllable thermal behavior.

4.1.3 On-chip interconnects: sparse event communication as the basis of system scalability

On-chip interconnects form a key architectural foundation that distinguishes neuromorphic chips from conventional AI accelerators. SNN computation is not a regular dense matrix operation; it is an irregular communication process triggered by neuronal spike events. Event routing, multicast delivery, congestion control, and cross-core communication latency therefore directly determine the performance, energy consumption, and real-time behavior of large-scale network mapping.

Among fabricated chips, two-dimensional mesh networks are a common on-chip interconnect structure. TrueNorth [21, 22], Tianjic [15], TianjicX [41], PAICORE 1.0 [23], Darwin3 [18], and Novena [46] all adopt two-dimensional mesh or mesh-like structures. This topology is regular, easy to implement physically, and suitable for scaling many-core arrays. Loihi [20] uses an asynchronous mesh NoC with dimension-ordered routing, emphasizing asynchronous event-driven communication. SpiNNaker [16, 17] uses a multicast packet NoC and a two-dimensional triangular torus topology, making it suitable for large-scale neuronal event broadcasting. DYNAPs [24] adopts a hierarchical packet NoC that combines local broadcast, tree routing, and two-dimensional mesh XY routing to support event communication at different hierarchy levels. PAICORE 2.0 [25] uses a five-level fat up-down quadtree NoC, while DualLearn [27] further introduces a 3D hexagonal NoC and six-direction low voltage differential signaling (LVDS) links. These designs reflect the evolution of neuromorphic interconnects from planar many-core arrays toward three-dimensional, package-level, and system-level communication.

For aerospace missions, the NoC is not a mere implementation detail. It is a key architectural factor that determines chip scalability, response latency, and power consumption. Space-object tracking, obstacle avoidance, attitude control, and fault response often require real-time processing across a large number of neuromorphic cores. As the network scale increases, inefficient event routing, long communication paths, or severe congestion can limit multi-core expansion and degrade closed-loop response speed. In addition, spacecraft operate under strict power and thermal constraints, and redundant spike/event communication directly increases energy consumption and heat dissipation. Therefore, NoC structures that support multicast, hierarchical routing, local communication, sparse-event compression, and scalable inter-core expansion are better aligned with the low-power, low-latency, high-reliability, and large-scale integration requirements of aerospace edge intelligence.

Three-dimensional on-chip interconnects and advanced packaging also deserve attention. Future spaceborne intelligent payloads may no longer consist of a single computing chip, but rather a heterogeneous system integrating sensors, memory, neuromorphic cores, conventional AI accelerators, and control processors. If event sensing, on-chip storage, and neuromorphic computation can be more tightly integrated through 3D stacking or package-level interconnects, board-level communication overhead can be reduced, system integration density can be improved, and energy efficiency can be enhanced under the strict volume and thermal constraints of space platforms.

4.1.4 Supported models: from pure SNNs to hybrid SNN/ANN/Transformer platforms

In terms of model support, early neuromorphic chips were mainly oriented toward spiking neuron models and biologically inspired neural dynamics. TrueNorth [21, 22], Loihi [20], ODIN [32], MorphIC [33], ROLLS [31], DYNAPs [24], IFAT [47], BrainScaleS [38, 39], and Neurogrid [37] primarily support LIF, IF, Izhikevich, AdEx, or conductance-based neuron models. Such chips are suitable for sparse event streams, temporal dynamics, and low-power sensing tasks, and they can be valuable for event-camera processing, anomaly detection, spike encoding, and neural-dynamics simulation.

However, aerospace intelligence workloads are rarely pure SNN workloads. A realistic onboard processing chain may include event-camera inputs, conventional image frames, infrared images, radar or LiDAR data, object-detection networks, trajectory-prediction networks, path-planning modules, and control-policy networks. Chips that support only SNNs may achieve high energy efficiency, but their generality and model compatibility are limited in complex tasks. In contrast, heterogeneous neuromorphic architectures that support SNNs, ANNs, CNNs, and even Transformers are better suited to multi-stage, multimodal, and multi-model cooperation in aerospace missions.

Tianjic [15] and TianjicX [41] reflect this shift by supporting ANN, SNN, and hybrid models. PAICORE 2.0 [25] supports enhanced LIF/Izhikevich models, ANN MAC/ReLU/pooling operations, and STDP learning. DualLearn [27] further supports SNNs, ANNs, and mixed precision including BF16, improving adaptability for heterogeneous training and inference. C-DNN [29] targets both CNNs and SNNs, while C-Transformer [30] extends neuromorphic computation toward DNN Transformers and spiking Transformers, bringing more complex sequence models and attention structures into the neuromorphic domain.

This hybrid model capability is particularly important for space platforms. SNNs are suitable for always-on sensing, event detection, and sparse temporal processing. ANNs and CNNs are suitable for high-accuracy image recognition and dense feature extraction. Transformer-like models may support more complex temporal modeling, multimodal fusion, and autonomous decision-making. If these models must be executed on several independent chips, board area, interface complexity, data-movement energy, and system verification difficulty will all increase. By contrast, unified or reconfigurable SNN/ANN hybrid architectures can switch computation modes within a single chip according to the task phase, providing a more compact, lower-power, and more easily integrated path for aerospace edge intelligence.

From this perspective, the value of hybrid compute fabrics is not simply that they support more model types, but that they allow different parts of an aerospace workload to be mapped to suitable computational primitives. Vision-based detection and pose estimation may still depend on CNN-like feature extraction or hybrid event-frame processing, whereas long-duration anomaly monitoring can benefit more from sparse SNN front ends with very low idle activity. For higher-level fusion and autonomous reasoning, Transformer-like or sequence-model components may be useful for integrating temporal context across sensors. A reconfigurable SNN/ANN fabric therefore provides a practical compromise between the efficiency of event-driven processing and the accuracy or expressiveness of dense neural models.

4.1.5 On-chip learning: a key boundary for in-orbit adaptation

On-chip learning is an important dimension that distinguishes neuromorphic chips from traditional fixed-function inference accelerators. This capability is especially important for aerospace missions. Satellites, deep-space probes, and planetary robots often face scarce samples, environmental drift, sensor aging, changing mission targets, and limited communication links. If models can only rely on ground-based training and periodic parameter uploads, they will struggle to meet the requirements of long-duration autonomous operation and adaptation to unknown environments. Therefore, whether neuromorphic chips can support low-power, few-shot, stable, and controllable in-orbit learning will become a major boundary for their adoption in aerospace systems.

Learning mechanisms in fabricated chips can be roughly divided into three categories. The first category includes biologically inspired local plasticity rules such as STDP, SDSP, S-SDSP, RSTDP, and three-factor learning. Loihi [20] and Loihi 2 [48] support programmable STDP or three-factor learning, ODIN [32] supports SDSP, MorphIC [33] supports S-SDSP, ROLLS [31] supports STDP-like LTP/LTD, STP, and SDSP, BrainScaleS [38, 39] supports STP/STDP, Darwin3 [18] supports configurable local learning rules, and PKU-STDP [49] is centered on STDP learning. These rules have low hardware overhead and strong locality, making them suitable for unsupervised learning, anomaly detection, environmental adaptation, and simple policy adjustment. Their limitation is that the learning objective is usually local and therefore difficult to use directly for global optimization of complex deep networks.

The second category consists of low-overhead online and incremental learning mechanisms. ReckOn [11] supports e-prop, ANP-I [36] supports sparse target propagation, ANP-G [42] supports STDP with lateral inhibition and few-shot class-incremental learning, ANP-L [43] supports adaptive-rate STDP and one/few-shot lifelong learning, ANP-R [44] supports multi-STDP and on-chip incremental learning, and ANP-O [45] supports STDP-based one/few-shot incremental learning. These methods usually achieve online updates with small chip area and low hardware overhead, making them suitable for few-shot recognition, class-incremental learning, and local scene adaptation. However, due to limitations in model capacity, training algorithms, and storage resources, their learning capability is usually difficult to extend directly to large-scale complex tasks.

The third category includes task-oriented training mechanisms. DualLearn [27] supports BP/STBP, C-DNN [29] supports sparse BP, and Park et al. [50] uses direct spike-only feedback. These methods are closer to deep-learning training flows and can improve accuracy on complex tasks, but they also introduce higher storage overhead, gradient-propagation cost, and control complexity. In aerospace platforms, learning must be evaluated not only by accuracy improvement, but also by power consumption, thermal stability, real-time behavior, fault tolerance, and safety constraints. Learning modes should therefore not be treated as simple add-ons to inference modes; they require dedicated co-design at the architecture, algorithm, and system-scheduling levels.

On-chip learning should be considered with a similar distinction. Local plasticity rules are attractive for low-risk adaptation, such as sensor recalibration, background drift compensation, or adjustment of anomaly thresholds, because they require little memory and can be implemented with local information. When the objective shifts toward few-shot class insertion or task-specific perception adaptation, stronger mechanisms such as prototype-based updates, supervised local-error signals, or forward-learning methods become more relevant. Backpropagation- or BPTT-like learning may offer higher accuracy for complex models, but its storage, computation, and energy costs make it more suitable for constrained and carefully supervised update windows than for continuous unrestricted in-orbit training.

Overall, current neuromorphic chips have demonstrated multiple on-chip learning routes, but there remains a clear gap before space-grade long-term autonomous learning can be achieved. A more realistic future direction may not be to reproduce full large-scale deep-network training on board, but rather to implement low-dimensional parameter updates, local plasticity regulation, event-driven memory updates, few-shot incremental learning, and safety-constrained policy tuning. Such mechanisms are better aligned with the low-power, high-reliability, and small-sample requirements of aerospace platforms.

4.1.6 Other recent advances

Beyond the representative architectures discussed above, recent fabricated neuromorphic processors further illustrate the diversification of application targets and hardware organizations. Speck [51] integrates asynchronous event sensing with spike-based dynamic computing for event-driven vision, while Braindrop [52] adopts a mixed-signal neuromorphic architecture based on a dynamical-systems-oriented programming model. NeuroREC [53] further demonstrates an efficient digital neuromorphic processor targeting radar emitter classification. At the circuit and architecture levels, Cho et al. [54] combine neuro-inspired pruning with an asynchronous network-on-chip for SNN acceleration, Liu et al. [55] exploit SRAM processing-in-memory together with on-chip unsupervised learning, Pu et al. [56] employ a reconfigurable neuron core and congestion-aware routing, Tang et al. [57] develop a low-complexity spike-count-based SNN architecture, and Fang et al. [58] improve accelerator efficiency by exploiting unstructured sparsity.

More recent designs also extend neuromorphic processing toward heterogeneous workloads and larger-scale systems. EA-HWP [59] supports CNN/SNN acceleration with hybrid weight precision, while a 28-nm optical-flow accelerator [60] demonstrates efficient event-camera-oriented processing with hybrid neural computation. Kuang et al. [61] further demonstrate a spike-based neuromorphic processor capable of efficient ANN implementation. At the system level, SpiNNaker 2 [62] extends the programmable many-core paradigm toward large-scale brain simulation and machine-learning workloads, whereas BrainScaleS-2 [63] combines accelerated neuromorphic computation with flexible plasticity mechanisms. Together, these designs broaden the architectural spectrum of fabricated neuromorphic processors.

4.1.7 Summary

In summary, Table 4 provides a comprehensive comparison of the state-of-the-art neuromorphic chips and SNN-oriented processors. Fabricated neuromorphic chips show a clear evolution from prototype validation toward system-level intelligent processing platforms. In terms of integration scale, they have progressed from early small learning cores with thousands to tens of thousands of neurons to hundred-thousand- and million-neuron platforms, with continuous improvements in synaptic capacity and on-chip storage. In terms of throughput and energy efficiency, related chips have expanded from GSOPS-level low-power SNN inference to TSOPS/TOPS-level heterogeneous computing, providing a stronger hardware foundation for complex edge-intelligence tasks. In terms of on-chip interconnects, two-dimensional mesh networks, multicast NoCs, hierarchical routing, quadtree structures, and 3D NoCs are all evolving, showing that sparse event communication has become a key factor in the scalability and real-time performance of neuromorphic systems. In terms of model support, neuromorphic chips are moving from single SNN processors toward hybrid SNN/ANN/CNN/Transformer platforms. In terms of on-chip learning, STDP, three-factor learning, e-prop, incremental learning, STBP, and BP jointly form a multi-level learning spectrum ranging from local plasticity to task-level training.

From the perspective of aerospace edge intelligence, neuromorphic chips offer three main advantages. First, event-driven and sparse computation can significantly reduce the power consumption of always-on sensing and temporal processing tasks, making them suitable for long-duration intelligent payloads on satellites, deep-space probes, and planetary robots. Second, near-memory/in-memory computation and on-chip event communication can reduce off-chip memory access and board-level data movement, improving system energy efficiency under constrained thermal conditions. Third, local learning, incremental learning, and few-shot adaptation provide a potential solution for in-orbit environmental changes, sensor drift, and recognition of unknown targets, suggesting that neuromorphic chips may serve not only as inference accelerators but also as adaptive computing cores in long-term autonomous systems.

Future evaluation of neuromorphic chips for aerospace edge intelligence should not focus solely on peak throughput or single-point energy efficiency. Instead, a task-loop-oriented evaluation framework should be established. Such a framework should include at least the following dimensions: low-power always-on sensing, complex model mapping, on-chip storage and communication efficiency, real-time response, in-orbit learning and adaptation, system-level reliability, and cooperation with conventional aerospace computing platforms. Only when neuromorphic chips demonstrate verifiable, reproducible, and engineering-level advantages across these dimensions can their application value in satellite intelligent payloads, deep-space exploration, space-object recognition, planetary robots, and autonomous spacecraft be fully realized.

Overall, neuromorphic chips have moved beyond the early stage of proving that SNNs can run at low power and entered a new stage of system-level architectural optimization for complex edge-intelligence tasks. For aerospace applications, the most promising future direction is not merely to pursue larger scale or higher peak throughput, but to build heterogeneous neuromorphic intelligent systems that can operate under limited power, limited thermal capacity, limited communication, and high-reliability constraints. Such systems should combine event sensing, sparse SNN computation, high-accuracy ANN/Transformer processing, on-chip incremental learning, and reliability-aware design to realize closed-loop intelligent processing from perception and recognition to decision-making and adaptation on space platforms.

4.2.1 Multimodal cognition: low-power continuous sensing for space stations and spacecraft

Multimodal cognition is one of the most natural entry points for neuromorphic chips in aerospace systems. Spacecraft, space stations, and planetary bases require long-term monitoring of visual, acoustic, vibration, thermal, gas, tactile, and physiological signals. These signals are often sparse, bursty, and strongly temporal, making them well suited for event-driven computation. Compared with frame-based sensors and periodically sampled processors, event cameras and spiking neural networks generate data and trigger computation only when changes occur, thereby reducing redundant data movement and matching the power, bandwidth, and thermal constraints of space platforms.

Event-based vision has already shown promising potential for space applications. Roffe et al. investigated neutron-induced single-event effects on neuromorphic event-based vision sensors and highlighted their asynchronous operation, clockless acquisition, high dynamic range above 120 dB, and sub-millisecond temporal precision. The study also provided early evidence of recovery behavior under radiation exposure [64]. For spacecraft perception, event-RGB fusion methods demonstrate that event cameras can complement RGB sensors under harsh illumination conditions such as glare, over-exposure, blooming, and lens flare, which are common challenges in rendezvous, docking, on-orbit servicing, and relative navigation [65]. The SPADES dataset further provides real and simulated event data for spacecraft pose estimation, offering a useful benchmark for evaluating event-based algorithms in space-relevant scenarios [66].

Beyond vision, many aerospace sensing tasks involve non-visual modalities. Equipment health monitoring can rely on vibration, acoustic, and current signals; astronaut health monitoring can combine electromyogram‌ (EMG), electroencephalogram‌ (EEG), electrocardiogram‌ (ECG), and motion sensors; and planetary robots require tactile, force, vision, and inertial feedback for grasping, assembly, and sampling. For such sparse, multimodal, and asynchronous signals, neuromorphic chips can serve as low-power front-end processors that perform event filtering, anomaly detection, feature compression, and coarse classification locally before passing high-value information to conventional CPUs, FPGAs, or high-precision AI accelerators. Therefore, the most realistic system architecture is not a fully neuromorphic replacement of all computation, but rather a heterogeneous stack consisting of event-based sensors, neuromorphic front-end processing, and conventional safety-supervisory processors.

For multimodal cognition, this suggests an architecture in which neuromorphic cores are used primarily for sparse front-end filtering, temporal feature extraction, and low-overhead adaptation. Such a front end can suppress redundant data, track slowly varying sensor baselines, and identify abnormal events before higher-precision processors are activated. When event streams must be combined with frame images, infrared measurements, radar, LiDAR, or inertial data, hybrid SNN/ANN fabrics become more useful because they can bridge asynchronous event representations and dense feature maps within a limited memory and communication budget.

4.2.2 Embodied AI: closed-loop control for UAVs, space robots, and planetary robots

Embodied AI is the application domain where the low-latency advantage of neuromorphic chips can be most directly exploited. Aircraft, rovers, robotic manipulators, and free-flying space robots must rapidly convert sensory input into motor actions, placing stringent requirements on end-to-end latency, power consumption, and robustness. The combination of event-based vision and SNNs naturally fits this requirement because event streams directly encode dynamic changes, while SNNs can perform sparse low-latency inference.

A representative demonstration is the fully neuromorphic vision-to-control pipeline for autonomous drone flight proposed by Paredes-Valles et al. The system uses a five-layer SNN with about 28.8k neurons to process raw event-camera data and generate low-level control actions. Running on Intel's Loihi processor, the system achieved an onboard execution frequency of 200 Hz with an energy cost of only about 27 microjoules per inference. This work shows that neuromorphic systems can enter the low-level control loop rather than acting merely as a perception front end [67]. Vitale et al. also demonstrated how an event-based vision algorithm can be mapped onto a neuromorphic chip for high-speed unmanned aerial vehicle (UAV) control and discussed the potential of on-chip learning for controller adaptation [68].

For aerospace systems, these results can be transferred to three major scenarios. First, they can support obstacle avoidance, landing, and terrain following for UAVs and Mars rotorcraft under high-dynamic lighting. Second, they can enable low-power visual odometry, local simultaneous localization and mapping (SLAM), manipulation, and dynamic target tracking for lunar or Martian base robots. Third, they can be used for sensing and navigation in free-flying robots inside space stations. However, existing neuromorphic drone experiments are still mostly ground-based or conducted on small aerial platforms. Before entering space-grade products, such systems must undergo radiation, thermal-vacuum, vibration, long-term reliability, and safety-supervision validation. Therefore, a near-term practical route is to use neuromorphic chips as auxiliary perception and local control modules rather than replacing safety-critical flight controllers.

For closed-loop embodied intelligence, low energy per inference is not sufficient by itself. Navigation, landing, manipulation, and free-flying control require predictable end-to-end timing from sensing to actuation, as well as local scheduling and supervisory logic that can monitor or override learned components. Architectures that couple neuromorphic cores with embedded CPU/RISC-V control are therefore relevant in this setting, because they can combine event-driven perception with runtime coordination, health monitoring, and safety-bounded adaptation.

4.2.3 Human-computer interaction: low-power front ends for astronaut assistance, health monitoring, and brain-machine interfaces

Human-computer interaction is a promising direction for neuromorphic chips in crewed spaceflight. During long-duration missions, astronauts face high workload, confined environments, communication delay, psychological stress, and health risks. Interactive systems must therefore operate continuously with low power, provide local real-time responses, and preserve privacy. Neuromorphic chips can be used for voice wake-up, gesture recognition, gaze and posture estimation, physiological anomaly detection, and neural-signal decoding, serving as front-end processors for astronaut assistants and health-monitoring systems.

Compared with conventional deep learning models, neuromorphic models offer three advantages in human-computer interaction. First, interaction signals are often event-like and temporal, such as speech onset, gesture transitions, EMG spikes, EEG rhythms, and abnormal heart-rate events. These signals are naturally compatible with spike encoding and event-driven processing. Second, crewed space systems have strict privacy and communication constraints, making local preprocessing and anomaly screening preferable to raw physiological data downlink. Third, on-chip learning may allow the system to adapt to the speech, motion, and physiological patterns of individual astronauts over long missions.

At present, aerospace validation in this direction is still indirect. Robotic assistants and human-robot interaction platforms such as Astrobee, CIMON, and Robonaut have already been explored on the International Space Station, but they are not themselves neuromorphic chip demonstrations. Recent Astrobee studies, however, show that the ISS provides a valuable platform for validating autonomous control and intelligent interaction in microgravity. For example, reinforcement-learning-based control has been demonstrated on NASA's Astrobee free-flying robot aboard the ISS [69]. This indicates that future neuromorphic human-computer interaction (HCI) systems could first enter non-safety-critical front-end tasks, such as astronaut state monitoring, voice or gesture wake-up, low-power anomaly alarms, and auxiliary robot perception, rather than life-support or critical operation chains.

4.2.4 Autonomous intelligent agents: onboard decision-making, resource management, and in-orbit autonomy

Autonomous intelligent agents represent the long-term goal of neuromorphic chips in space systems. As satellite constellations, deep-space probes, and on-orbit servicing missions become more complex, spacecraft will need to perform mission planning, resource allocation, anomaly handling, and local decision-making under communication delay or link interruption. In this context, the value of neuromorphic chips lies not only in low-power inference, but also in event-driven decision-making, online learning, and continual adaptation.

One representative example is onboard radio resource management for satellite communications. Ortiz et al. applied SNNs implemented on Intel Loihi 2 to satellite communication resource management and compared the approach with a CNN baseline running on a Xilinx Versal VCK5000 platform. For relevant workloads, the Loihi 2 SNN achieved comparable or higher accuracy while reducing power consumption by more than 100x relative to the CNN reference platform [12]. This result suggests that neuromorphic chips are not limited to vision tasks; they can also support scheduling, communication, and resource-optimization problems on board spacecraft.

For space robotics and on-orbit servicing, recent Astrobee-related studies show a validation pathway from simulation to ground testing and finally to in-orbit autonomous control [70]. The APIARY experiment further reports reinforcement-learning-based control of a free-flying robot on the ISS, illustrating the need for future space agents to support terrestrial training, in-orbit deployment, and task-level adaptation [69]. Although these demonstrations are not implemented on neuromorphic chips, they define mission carriers where neuromorphic processors could provide low-power policy inference, event-driven state estimation, anomaly detection, local planning, and safety-constrained monitoring.

A reasonable development path for neuromorphic autonomous agents can be divided into three stages. The first stage is to validate low-power inference in onboard edge processing and resource management, such as cloud detection, target filtering, communication beam scheduling, and interference classification. The second stage is to validate closed-loop perception-decision-control capabilities in space robots, rovers, and free-flying platforms, including navigation, obstacle avoidance, grasping, assembly, and inspection. The third stage is to combine on-chip learning with safety-supervisory mechanisms to explore in-orbit incremental learning, task adaptation, and multi-agent collaboration. Only when neuromorphic chips demonstrate energy efficiency, real-time performance, robustness, and verifiability at the mission level can their role evolve from interesting low-power hardware to deployable infrastructure for autonomous space intelligence.

These stages also imply that neuromorphic validation should progress through workload-specific evidence. Continuous monitoring can first establish the benefit of low-idle-power event-driven processing and local adaptation. Perception experiments can test whether hybrid event-frame or SNN/CNN mappings improve the energy-accuracy trade-off. Control demonstrations should emphasize deterministic scheduling, communication latency, and fault-aware operation. Autonomous-agent studies can then evaluate whether heterogeneous computation and constrained on-chip learning improve long-duration decision-making under limited ground support. Such evidence would provide a more convincing basis for aerospace adoption than a single aggregate performance benchmark.

Taken together, Figure 7 illustrates the key application domains where neuromorphic chips have shown validation potential in space missions.

Figure 7 Aerospace validation cases for neuromorphic processors, covering multimodal sensing, closed‑loop control, astronaut assistance, and autonomous onboard decision‑making. Some elements of this graphic (the icons) were created using GPT-5.6 (OpenAI). For image credits, please see the Disclosing the use of AIGC section of this article.