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Research Progress on Fabrication of High-Purity Tantalum Targets for Advanced Process Chip AITranslate

1.School of Materials Science and Engineering,Zhejiang University,Hangzhou 310000,China
2.Konfoong Materials International Co.,Ltd.,Ningbo 315400,China
3.College of Chemical and Material Engineering,Quzhou University,Quzhou 324000,China
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Abstract AITranslate

In integrated circuits with feature sizes below 90 nm,Cu interconnects has replaced Al as the new interconnect metal due to their advantages of lower resistivity,higher melting point,superior resistance to stress migration,and improved resistance to electromigration. When Cu was directly interconnected with Si in integrated circuits,it could lead to severe diffusion and generate interface thermal stress at above 120 ℃ and could result in the failure of wire electrical performance and the delamination of the interface. Therefore,it is necessary to incorporate Ta diffusion barrier layer between Cu and Si. Ta/TaN barrier layer effectively inhibited the diffusion of Cu and Si in high-temperature environments. On the other hand,it exhibits excellent adhesion to various layers and low contact resistance. Moreover,TaN demonstrated the ability to fill grain boundaries while maintaining a high level of thermal stability up to 650 ℃. These characteristics make Ta/TaN layer one of the optimal choices for constructing a diffusion barrier layer between Cu and Si. The preparation of the diffusion barrier layer Ta/TaN required the use of physical vapor deposition (PVD)techniques. However,the quality of the raw materials,particularly ultra-high purity Ta targets are used as a crucial material in PVD,could significantly affect the uniformity of the deposited film thickness and electrical performance due to issues such as purity,grain size,and texture gradient uniformity,this will have an impact on the yield of advanced process chips (sub-28 nm technology nodes). As integrated circuit chip fabrication technology advances to sub-28 nm technology nodes,the number of metal layers in logic circuits continues to increase,while the wire widths become increasingly narrow,and the requirements for barrier layer thickness also become thinner. In this review,it was crucial for ultra-high purity Ta targets to minimize texture and grain size variation gradients in order to achieve a more uniform distribution of the microstructure. However,Ta targets used in 130 and 90 nm processes would no longer meet the requirements of advanced process chips. The complete fabrication process for ultra-high purity Ta targets included the preparation of high-purity Ta powder,ingot casting,sintering,electron beam (EB)casting,forging,rolling,heat treatment,and machining. Both domestic and international Ta producers sourced the raw material for Ta products from Ta mines located in Africa and Australia. The raw material used for producing Ta powder was predominantly potassium tantalum fluoride (K2TaF7),and the acquisition of mineral resources was not considered challenging. Therefore,the key technology in the industrial chain of Ta targets for advanced process chips lay in the fabrication of target blanks that met the application requirements. The main focus and challenges within the complete fabrication process revolved around the purification of ultra-high purity Ta and the thermomechanical processing (TMP)of target blanks,which included forging,rolling,and recrystallization processes. Furthermore,it was essential to ensure the consistency of the microstructure among target blanks during mass production. The purification of Ta served as the starting point in the entire process,the most widely used method was the sodium reduction process using K2TaF7 as the raw material to produce high-purity Ta powder. Subsequently,the high-purity Ta powder was ingot formation and sintered in a vacuum furnace. The next step involved EB melting,which further purified the Ta and could achieve purities exceeding 99.999%(5N),meeting the application requirements for diffusion barrier layers in advanced process chips. However,due to the coarse grain size and uncontrolled crystal orientation of Ta obtained through EB melting,it could not be used without undergoing TMP. Thermal and multi-directional forging was beneficial for improving the uniformity of the microstructure and reducing texture gradients. For rolling,cross-rolling could eliminate the anisotropy generated by unidirectional rolling of Ta and ensure a more uniform distribution of texture on the rolled surface. Additionally,while cold rolling could more effectively achieve the desired texture,hot rolling activates more slip systems,resulting in smaller texture gradients. The rolling energy was retained within the Ta metal as stored energy and served as the driving force for recrystallization when the temperature increased during the recrystallization annealing stage. However,due to the different nucleation positions and mechanisms,the recrystallization rates of Ta in different regions of the target blanks vary,resulting in unavoidable texture gradients. Moreover,due to the high cost of ultra-high purity Ta and the high sensitivity of the later-stage processes to the preceding stages,the development of mature processes required significant investment,resulting in only a few companies worldwide having complete mastery of the entire fabrication process. This situation persisted despite the rapid development of the chip manufacturing industry. To further develop and optimize ultra-high purity Ta targets for integrated circuit applications and explore the use of Ta as a diffusion barrier layer in advanced process chips,three innovative research directions had been proposed:1)The sputtering lifetime of the 0.65-inch-thick Ta targets was increased by more than 3 times compared to the 0.25-inch targets. The increase in target thickness reduced the frequency of machine preventive maintenance (PM),and improved the utilization of expensive ultra-high purity Ta material,thereby reducing the cost of chip fabrication and enhancing economic efficiency. Therefore,it was necessary to redesign the ultra-high purity Ta TMP process to develop and optimize ultra-high lifetime,high thickness (0.65-inch)Ta targets that offer higher economic efficiency and material utilization rates. 2)By researching and improving the PVD process parameters of Ta targets,it was possible to fabricate α-Ta layers with enhanced diffusion barrier capabilities,thereby further improving the performance of advanced process chips. 3)Numerical simulations indicated that multiple passes of equal channel angular pressing refined the grain structure of tantalum,offering potential to improve the grain size and texture distribution of ultra-high-purity targets in advanced chip manufacturing.

KeyWords AITranslate

ultra-high purity tantalum sputtering target texture control very large-scale integration advanced process chip tantalum barrier layer material

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Basic Information:

DOI:10.13373/j.cnki.cjrm.XY23040019

Chinese Library Classification Number:TG146.4+16

Citation Information:

In integrated circuits with feature sizes below 90 nm,Cu interconnects has replaced Al as the new interconnect metal due to their advantages of lower resistivity,higher melting point,superior resistance to stress migration,and improved resistance to electromigration. When Cu was directly interconnected with Si in integrated circuits,it could lead to severe diffusion and generate interface thermal stress at above 120 ℃ and could result in the failure of wire electrical performance and the delamination of the interface. Therefore,it is necessary to incorporate Ta diffusion barrier layer between Cu and Si. Ta/TaN barrier layer effectively inhibited the diffusion of Cu and Si in high-temperature environments. On the other hand,it exhibits excellent adhesion to various layers and low contact resistance. Moreover,TaN demonstrated the ability to fill grain boundaries while maintaining a high level of thermal stability up to 650 ℃. These characteristics make Ta/TaN layer one of the optimal choices for constructing a diffusion barrier layer between Cu and Si. The preparation of the diffusion barrier layer Ta/TaN required the use of physical vapor deposition (PVD)techniques. However,the quality of the raw materials,particularly ultra-high purity Ta targets are used as a crucial material in PVD,could significantly affect the uniformity of the deposited film thickness and electrical performance due to issues such as purity,grain size,and texture gradient uniformity,this will have an impact on the yield of advanced process chips (sub-28 nm technology nodes). As integrated circuit chip fabrication technology advances to sub-28 nm technology nodes,the number of metal layers in logic circuits continues to increase,while the wire widths become increasingly narrow,and the requirements for barrier layer thickness also become thinner. In this review,it was crucial for ultra-high purity Ta targets to minimize texture and grain size variation gradients in order to achieve a more uniform distribution of the microstructure. However,Ta targets used in 130 and 90 nm processes would no longer meet the requirements of advanced process chips. The complete fabrication process for ultra-high purity Ta targets included the preparation of high-purity Ta powder,ingot casting,sintering,electron beam (EB)casting,forging,rolling,heat treatment,and machining. Both domestic and international Ta producers sourced the raw material for Ta products from Ta mines located in Africa and Australia. The raw material used for producing Ta powder was predominantly potassium tantalum fluoride (K2TaF7),and the acquisition of mineral resources was not considered challenging. Therefore,the key technology in the industrial chain of Ta targets for advanced process chips lay in the fabrication of target blanks that met the application requirements. The main focus and challenges within the complete fabrication process revolved around the purification of ultra-high purity Ta and the thermomechanical processing (TMP)of target blanks,which included forging,rolling,and recrystallization processes. Furthermore,it was essential to ensure the consistency of the microstructure among target blanks during mass production. The purification of Ta served as the starting point in the entire process,the most widely used method was the sodium reduction process using K2TaF7 as the raw material to produce high-purity Ta powder. Subsequently,the high-purity Ta powder was ingot formation and sintered in a vacuum furnace. The next step involved EB melting,which further purified the Ta and could achieve purities exceeding 99.999%(5N),meeting the application requirements for diffusion barrier layers in advanced process chips. However,due to the coarse grain size and uncontrolled crystal orientation of Ta obtained through EB melting,it could not be used without undergoing TMP. Thermal and multi-directional forging was beneficial for improving the uniformity of the microstructure and reducing texture gradients. For rolling,cross-rolling could eliminate the anisotropy generated by unidirectional rolling of Ta and ensure a more uniform distribution of texture on the rolled surface. Additionally,while cold rolling could more effectively achieve the desired texture,hot rolling activates more slip systems,resulting in smaller texture gradients. The rolling energy was retained within the Ta metal as stored energy and served as the driving force for recrystallization when the temperature increased during the recrystallization annealing stage. However,due to the different nucleation positions and mechanisms,the recrystallization rates of Ta in different regions of the target blanks vary,resulting in unavoidable texture gradients. Moreover,due to the high cost of ultra-high purity Ta and the high sensitivity of the later-stage processes to the preceding stages,the development of mature processes required significant investment,resulting in only a few companies worldwide having complete mastery of the entire fabrication process. This situation persisted despite the rapid development of the chip manufacturing industry. To further develop and optimize ultra-high purity Ta targets for integrated circuit applications and explore the use of Ta as a diffusion barrier layer in advanced process chips,three innovative research directions had been proposed:1)The sputtering lifetime of the 0.65-inch-thick Ta targets was increased by more than 3 times compared to the 0.25-inch targets. The increase in target thickness reduced the frequency of machine preventive maintenance (PM),and improved the utilization of expensive ultra-high purity Ta material,thereby reducing the cost of chip fabrication and enhancing economic efficiency. Therefore,it was necessary to redesign the ultra-high purity Ta TMP process to develop and optimize ultra-high lifetime,high thickness (0.65-inch)Ta targets that offer higher economic efficiency and material utilization rates. 2)By researching and improving the PVD process parameters of Ta targets,it was possible to fabricate α-Ta layers with enhanced diffusion barrier capabilities,thereby further improving the performance of advanced process chips. 3)Numerical simulations indicated that multiple passes of equal channel angular pressing refined the grain structure of tantalum,offering potential to improve the grain size and texture distribution of ultra-high-purity targets in advanced chip manufacturing.

quote

GB/T 7714-2015 [1] Qitao Huang, Lijun Yao, Weihua Zhong, et al. Research Progress on Fabrication of High-Purity Tantalum Targets for Advanced Process Chip[J]. Chinese Journal of Rare Metals, 2025, 49(5): 669-678. DOI:10.13373/j.cnki.cjrm.XY23040019.
MLA [1] Qitao Huang, et al., "Research Progress on Fabrication of High-Purity Tantalum Targets for Advanced Process Chip." Chinese Journal of Rare Metals, vol. 49, no. 5, 2025, pp. 669-678, https://doi.org/10.13373/j.cnki.cjrm.XY23040019.
APA [1] Qitao Huang, Lijun Yao, Weihua Zhong, Qianjing Yuan, Yanfang Wu, & Hui Yang. (2025). Research Progress on Fabrication of High-Purity Tantalum Targets for Advanced Process Chip. Chinese Journal of Rare Metals, 49(5), 669-678. https://doi.org/10.13373/j.cnki.cjrm.XY23040019
IEEE [1] Qitao Huang, Lijun Yao, Weihua Zhong, Qianjing Yuan, Yanfang Wu, and Hui Yang, "Research Progress on Fabrication of High-Purity Tantalum Targets for Advanced Process Chip," Chinese Journal of Rare Metals, vol. 49, no. 5, pp. 669-678, 2025, doi: 10.13373/j.cnki.cjrm.XY23040019. keywords: {ultra-high purity tantalum;sputtering target;texture control;very large-scale integration;advanced process chip;tantalum barrier layer material}