Cryogenic Si/SiGe Heterostructure Flash Memory Devices Cryogenic Si/SiGe Heterostructure Flash Memory Devices AITranslate
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We demonstrate a cryogenic flash memory on an undoped Si/SiGe heterostructure by the modulation of its charge distributions. Two charge states are created using a Si cap layer as a charge storage layer and manipulated by electron tunneling between the Si cap and a buried Si quantum well (QW). The device is programmed by increasing the gate bias to enhance the tunneling rates of electrons in the buried Si QW to the Si cap. The erasing step is performed by applying a negative gate bias to deplete electrons trapped in the Si cap layer via tunneling to the buried Si QW. The device has advantages over conventional flash memory devices, since the programming and erasing operations are executed via electron tunneling across the crystalline SiGe layer. We demonstrate an endurance of 104 cycles and a retention time of 104 seconds with a memory window of threshold voltages of 1.4 V at 4 K, and the device is functional at temperatures up to 40 K.
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DOI:https://doi.org/10.1021/acsaelm.2c00364
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We demonstrate a cryogenic flash memory on an undoped Si/SiGe heterostructure by the modulation of its charge distributions. Two charge states are created using a Si cap layer as a charge storage layer and manipulated by electron tunneling between the Si cap and a buried Si quantum well (QW). The device is programmed by increasing the gate bias to enhance the tunneling rates of electrons in the buried Si QW to the Si cap. The erasing step is performed by applying a negative gate bias to deplete electrons trapped in the Si cap layer via tunneling to the buried Si QW. The device has advantages over conventional flash memory devices, since the programming and erasing operations are executed via electron tunneling across the crystalline SiGe layer. We demonstrate an endurance of 104 cycles and a retention time of 104 seconds with a memory window of threshold voltages of 1.4 V at 4 K, and the device is functional at temperatures up to 40 K.
quote
| GB/T 7714-2015 | [1] WeiChih Hou, NaiWen Hsu, TzMing Wang, et al. ACS Applied Electronic Materials, 2022(4). DOI:10.1021/acsaelm.2c00364. |
| MLA | [1] WeiChih Hou, et al., ACS Applied Electronic Materials, no. 4, 2022, https://doi.org/10.1021/acsaelm.2c00364. |
| APA | [1] WeiChih Hou, NaiWen Hsu, TzMing Wang, ChiaYou Liu, HsiangShun Kao, MiinJang Chen, & JiunYun Li. (2022). ACS Applied Electronic Materials(4). https://doi.org/10.1021/acsaelm.2c00364 |
| IEEE | [1] WeiChih Hou, NaiWen Hsu, TzMing Wang, ChiaYou Liu, HsiangShun Kao, MiinJang Chen, and JiunYun Li, ACS Applied Electronic Materials, no. 4, 2022, doi: 10.1021/acsaelm.2c00364. keywords: {cryogenic memory Si/SiGe heterostructure flash surface tunneling} |
