Vacuum Lamination of Polymer Gate Dielectric Layers for Facile Fabrication of Organic Transistors Vacuum Lamination of Polymer Gate Dielectric Layers for Facile Fabrication of Organic Transistors AITranslate

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DOI：https://doi.org/10.1021/acsaelm.2c00591

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A vacuum lamination method has been considered as a practical alternative to expensive and time-consuming layer deposition methods for fabricating the polymer dielectric layers of organic thin film transistors (OTFTs). Using this method, different layers of materials can be readily combined under a weak vacuum. However, poor adhesion at the interface between the organic semiconductor layer and laminated polymer dielectric layer limits the application of the vacuum lamination method only to the fabrication of organic single-crystal transistors; the fabricated transistors were not practical and operated only when a diaphragm pump was used to maintain the intimate adhesion between the single crystal and the polymer dielectric layer. In this work, we developed an advanced vacuum lamination strategy for fabricating a thin polymer dielectric layer on an arbitrary polymer semiconductor thin film. We observed that pasting glue at the rim of the sample and applying thermal annealing in a vacuum resulted in a strong intimate contact between the semiconductor and dielectric layer interface by efficiently removing air bubbles at the interface. The fabricated vacuum-laminated heterojunction structure was used in OTFTs and exhibited excellent electrical characteristics with a small number of trap sites. We believe that the proposed method would provide a facile research platform for studying polymer semiconductor/polymer dielectric layer heterojunctions.