High-κ Gate Dielectric on Tunable Tensile Strained Germanium Heterogeneously Integrated on Silicon: Role of Strain, Process, and Interface States AITranslate

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DOI：https://doi.org/10.1021/acsaelm.3c00568

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Tensile strained germanium (ε-Ge) layers heterogeneously integrated on Si substrates are of technological importance for nanoscale transistors and photonics. In this work, the tunable tensile strained (0% to 1.2%) ε-Ge layers were grown by solid source molecular beam epitaxy using GaAs and linearly graded InxGa1–xAs as intermediate buffers, and their structural and metal-oxide semiconductor capacitor (MOS-Cs) properties were analyzed as a function of strain and process conditions. X-ray topography measurements displayed no visible thermal crack and a low thermal stress of ∼50 MPa. Temperature dependent strain relaxation properties, studied by X-ray and Raman analyses, confirmed that the tensile strain amount of 1.2% was well preserved within the ε-Ge layer when annealed up to 550 °C. Further, transmission electron microscopic study revealed a good quality 1.2% strained ε-Ge/In0.17Ga0.83As heterointerface. In addition, unstrained Ge (0% ε-Ge) MOS-Cs with atomic layer deposited Al2O3 and thermally grown GeO2 composite gate dielectrics of varying oxidation times (0.25–7.5 min) at 550 °C exhibited a low interface state density (Dit) of ∼2.5 × 1011 eV–1 cm–2 at 5 min oxidation duration. The minimum oxidation time needed for good capacitance–voltage (C–V) characteristics on 0.2% ε-Ge is inadequate to accomplish similar C–V characteristics on 1.2% ε-Ge MOS-C, due to the higher strain field impeding the formation of the GeO2 interface passivation layer at lower oxidation duration. In addition, with the trade-off between the minimum Dit and minimum equivalent oxide thickness values, ∼1.5 min is found to be an optimum oxidation time for good quality 1.2% ε-Ge MOS-C. The minimum Dit values of 1.36 × 1011 and 2.06 × 1011 eV–1 cm–2 for 0.2% and 1.2% ε-Ge, respectively, were determined for 4 nm Al2O3 with 5 min thermal oxidation at 550 °C. Therefore, the successful monolithic integration of tunable tensile strain Ge on Si with structural defects and MOS-Cs analyses offer a path for the development of tensile strained Ge-based nanoscale transistors.