Cost-effective and high-speed implementation of brain-like spiking neural network with encoding architectures on FPGA

Zhen Cao¹ ✉ Ziyi Zhang¹Qi Sun¹Biao Hou¹ ✉ Licheng Jiao¹Yintang Yang¹

School of Artificial Intelligence and School of Microelectronics, Xidian University, Shaanxi 710071, China

Abstract： The spiking neural network (SNN) is the third generation of neural networks, valued for its biological interpretability, hardware compatibility, and low power consumption. While field programmable gate array (FPGA), based SNN accelerators show promise with their intelligent design and low power consumption, existing models lack a crucial spiking encoding module. This leads to increased pre-processing time on the CPU. To address these issues, this paper proposes an FPGA-based SNN accelerator with a spiking encoding module. This innovation reduces CPU pre-processing time by threefold without adding FPGA processing time. Achieving 92.62% accuracy on the MNIST dataset using LIF spiking neurons at 0.675 W, the accelerator outperforms CPU and GPU, being 14× faster and 2.5× faster, respectively, and more power-efficient with minimal resource usage. Given its pixel input, it can be seamlessly embedded in real-time classification systems for efficient classification and detection.

Keywords： SNN accelerator; FPGA; spiking encoding; low-power; neuromorphic computing

Received： 2023-11-25

1 Introduction

Hailed as the third generation of neural networks, spiking neural network (SNN) is a neural network model that mimics the biological nervous system and simulates the way information is transmitted between neurons in the brain through spikes [1], as shown in Fig. 1. During the latter decades of the 20th century, specifically in the 1980s and 1990s, a burgeoning interest in the theoretical underpinnings and learning algorithms of SNNs emerged among researchers. A pivotal milestone was reached in 2003 when Izhikevich introduced an innovative spiking neuron model [2] that significantly streamlined computations while maintaining remarkable fidelity in simulating a wide array of neuronal behaviors. This groundbreaking proposal laid the groundwork for more practical and effective implementations of SNNs.

Figure 1 Spiking neural network model.

SNN is celebrated for its advanced capability to simulate biological neural processes and its inherent compatibility with event-driven hardware architectures, which enables a form of computation that parallels the human brain's efficiency in terms of both low power consumption and high-performance processing. By virtue of these attributes, SNNs are uniquely positioned to emulate the brain's energy-efficient information processing mechanisms, thereby fostering an innovative paradigm shift towards neuromorphic computing systems. It represents a crucial area of study in brain-like computing systems [3, 4]. In the 1990s and 2000s, researchers developed specialized neuromorphic chips like SpiNNaker [5], TrueNorth [6], Darwin1,2 [7, 8], Loihi1,2 [9, 10], Tianjic [11], TianjicX [12] to simulate SNN models. These chips, equipped with parallel computing capabilities and low power consumption, enable practical applications of SNN.

Application-Specific integrated circuit (ASICs) offer advantages like smaller size, lower power consumption, and higher integration, but they come with longer design cycles, higher costs, and no post-completion modifications. In contrast, the semi-custom design method shortens development cycles, significantly reduces costs, and allows for convenient design modifications, making it ideal for mass production. Consequently, field programmable gate arrays (FPGAs) are increasingly chosen by researchers for SNN acceleration. Leveraging FPGA flexibility and parallel computing power enables the creation of high-performance, real-time processing, and low-power consumption systems [13]. Notably, Neil et al. introduced Minitaur, an FPGA-based, low-power, high-performance, event-driven SNN accelerator [14]. Zhang et al. proposed an asynchronous SNN accelerator with 1024 neurons and 1 million synapses [15]. Other studies include Huang et al.'s low-power SNN design for radioisotope identification [16], Khodamoradi et al.'s streaming SNN (S2N2) architecture on FPGA [17], and Gao et al.'s application of the MLIF model to SNN with basal dendrites, apical dendrites, and somas [18].

However, the FPGA-based SNN accelerators discussed earlier require spike trains as input, leading to CPU-intensive pre-processing such as spiking encoding for image classification. This CPU-centric approach not only consumes more time and power but also contrasts with the efficiency achieved by encoding directly on the FPGA. To overcome this challenge, we proposes an inventive FPGA-based SNN accelerator implementation with integrated spiking encoding in this paper. Significantly, this method drastically reduces CPU pre-processing time by threefold without adding extra processing time on the FPGA. Distinguishing itself from prior methodologies, our approach excels in judicious resource utilization, diminished power consumption, and expedited image inference. Notably, the pixel-based input structure of the system seamlessly integrates into real-time classification systems, promising efficient and swift classification and detection.

2 Materials and methods

2.1 Spiking encoding

In the SNN, information propagates through spikes, and spiking encoding technology plays a pivotal role in translating information into spike trains. This key technology encompasses common encoding techniques, categorized into rate encoding and temporal encoding [19]. This paper employs a widely used method for generating spike trains known as Poisson distributed spike encoding [20, 21]. The Poisson encoding method falls under the category of rate encoding and transforms input data into spike trains with an issuance distribution adhering to the Poisson process. Specifically, $P (X = k) = \frac{λ^{k}}{k!} e^{- λ}$ (1)where, P denotes the probability of event Xoccurring k times, and the parameter λ is the average number of occurrences of random events per unit time or unit area.

We performed Poisson encoding on the image over 20 timestep, and Fig. 2(a) represents the spike trains at t = 1, 5, 10, 15, 20, showing that the Poisson encoding is time-independent. Superimposing the spike trains in 20 timesteps, Fig. 2(b) shows the cumulative effect at t = 1, 5, 10, 15, 20. It can be seen that the original image can be efficiently reconstructed through the repeated overlay of Poisson encoding.

Figure 2 Poisson encoding: (a) spike train encoded image with different timestep; (b) cumulative effect superimposed encoding image in 20 timestep.

In practical implementation, Poisson spike trains are commonly generated by comparing scaled pixels to random numbers. The FPGA's Poisson encoding module utilizes a pseudo-random number generator (PRNG) and a comparer. In Fig. 3, the PRNG is realized through a 16-bit linear shift register employing three XOR gates.

Figure 3 Circuit diagram for Poisson encoding.

FPGA systems operating with spike trains as input currently necessitate CPU-driven encoding processing and the FPGA input is serialized. In Fig. 4, the introduction of an encoding module to the FPGA system maintains the same input length as the prior system. However, with the addition of parallel encoding processing and neuron calculations, there is minimal extra FPGA processing time. Consequently, incorporating an encoding module into the FPGA system reduces the encoding time in pre-processing without escalating FPGA processing time. Moreover, in the second system, pixels could originate from a sensor like a camera, allowing direct integration into real-time systems without the need for pre-processing.

Figure 4 The distinction between CPU-based encoding and FPGA-based encoding is depicted: (a) encoding on the other device; (b) encoding on the FPGA.

2.2 Spiking neuron

The primary distinction between SNN and artificial neural networks lies in their neurons. Spiking neurons closely mimic human neuron connections. Neurophysiologists have devised various models to capture the dynamic electrical potential of working neurons, serving as the fundamental units of SNN and determining the network's core dynamics. The realization of SNN is intricately tied to the evolution of spiking neurons, with models such as the Hodgkin-Huxley model [22] and the Izhikevich model [2] closely resembling biological neurons. However, their intricate hardware circuitry renders them less suitable for practical hardware deployment. In contrast, the IF model [23, 24] and the integrate-and-fire (LIF) model [25, 26], while not as intricate as their predecessors, offer simplicity in calculations and are more amenable to hardware deployment. This paper employs the LIF neuron model, described by the following equation as $τ_{m} \frac{d V (t)}{d t} = - (V (t) - V_{r e s}) + R I (t)$ (2)where τ_m epresents the delay constant, V(t) signifies the instantaneous value of the neuronal membrane potential at time t, and V_res epresents the resting value, the membrane potential when there is no input.

As Eq. (2) is in the differential form, and FPGA processes digital signals exclusively, it is discretized and organized Eq. (2) as follows: $V (t + 1) = V (t) + (R I (t) - (V (t) - V_{r e s})) / τ_{m}$ (3)where I(t) represents the input spikes received by the neuron, correlating to the synapses in the neural network, Eq. (3) can be modified to $V (t + 1) = V (t) + (\sum_{i} W_{i} S_{i} - (V (t) - V_{r e s})) / τ_{m}$ (4)where i is the ith synapse connected to the neuron, W_i is the weight corresponding to the ith synapse, and S_i indicates whether the current timestep of the i^th synapse has an input spike, which is 1 or 0 otherwise. In this work, the τ_m is 2 and the V_res is 0.

The circuit diagram for the computation and update of the LIF neuron is illustrated in Fig. 5.

Figure 5 LIF neuron circuit diagram.

The neuron initially aggregates the weights corresponding to spikes at the same timestep t. Subsequently the neuron calculates the current membrane potential by incorporating the previous moment's membrane potential and updates the potential. Following the computation, the neuron compares the membrane potential with the threshold. If the membrane potential exceeds the threshold, the neuron generates a spike and resets the membrane potential to the reset potential.

2.3 Network

In this paper, the MNIST dataset is utilized for testing, comprising 60,000 training sets and 10,000 test sets. The architecture of a 784-10 fully connected layer SNN is depicted in Fig. 6. Spike trains serve as input to the network, and communication between each layer employs the address event representation (AER) protocol [27]. Following computation, each neuron in the output layer determines whether it generates a spike in each timestep. By tallying the spikes, the category associated with the neuron producing the most spikes after T timestep is considered as the classification result. Network training is conducted using the PyTorch and SpikingJelly [28] frameworks. Optimal weights are obtained and quantized into 16-bit fixed-point numbers, with the specific quantization method being W_i=w_i·2β. Where β is 15 and the 16^th bit is the sign bit.

Figure 6 Spiking fully connected network architecture.

2.4 System architecture

The system architecture is shown in Fig. 7. Initially, the weight ROM initializes the weights of each neuron, and data is allowed to entry only after completion of this initialization. Subsequently, as data is entered, the spike_encoder module generates spike trains by encoding pixel value using the Poisson encoding method. The network calculates the spike trains at each timestep, producing corresponding output spikes. Concurrently, the spike_counter module tallies the spikes generated by the respective neurons. After T timestep, the max_comparer module identifies the neuron generating the most spikes as the output. Prior to the arrival of the next set of data, the membrane potential and spike count of a neuron are reset to zero. This iterative procedure persists until the exhaustive evaluation of the entire dataset has been accomplished.

Figure 7 System architecture.

3 Results and discussion

All tests in this section are conducted on the MNIST test dataset, and they are performed at a clock frequency of 100 MHz on the FPGA.

3.1 Test for Poisson encoding

We evaluate the network performance on CPU, GPU, ASIC, and FPGA, and the results are presented in Table 1.

Table 1 Comparations with other platforms.

Platform	Type	Time (s)	Accuracy (%)	Power (W)
This work	FPGA	1.5693	92.62	0.675
i7-8565U	CPU	22.3933	92.69	56.1
RTX 3060 (batch_size=64)	GPU	4.0458	92.69	58.2
TrueNorth [6]	ASIC	2.1867	93.00	0.18
Minitaur [14]	FPGA	10.8755	92.00	1.5

Analyzing the data in Table 1, it is evident that the FPGA system outperforms the CPU implementation by 14 times and the GPU implementation by 2.5 times, with a negligible 0.07% reduction in accuracy. Notably, the power consumption of this work, at 0.675 W, is significantly lower than that of the CPU and GPU implementations. Moreover, in comparison to another FPGA-based accelerator named Minitaur, this work exhibits superior speed and lower power consumption. Upon examining the data presented in Table 2, it becomes evident that regardless of the varying timestep, the FPGA accelerator consistently demonstrates a speed improvement of approximately 14 times over the CPU.

Table 2 The accuracy and using time of FPGA system with different timesteps.

Timestep	Accuracy on PC (%)	Time on PC (s)	Accuracy on FPGA (%)	Time on FPGA (s)
100	93.06	102	93.00	7.6354
20	92.69	22.3933	92.62	1.5695
10	91.85	12.4128	91.85	0.7861
5	90.77	7.2795	90.82	0.3941

To assess the performance of the PRNG in our design, we conduct a comparison with the {$random} function in Verilog. B. Fang et al. [29] implemented the fixed uniform spike generation algorithm in the spiking convolutional neural network (SCNN) on FPGA, and in another work [30], H. Fang achieved an SCNN architecture with time encoding also based on FPGA. Our design is then compared with these two works.

Analyzing the data in Table 3, it is observed that employing the PRNG as the Poisson encoding module results in a 0.06% higher accuracy and a 0.1% lower power consumption compared to using the {$random} function. While our design, focused on image classification using SCNN, exhibits lower accuracy compared to the two referenced works, it is noteworthy that our system is three times faster and consumes 6–7 times less power than the other two designs. In terms of speed and power efficiency, our design stands out.

Table 3 Test for Poisson encoding module.

	Accuracy (%)	Time (s)	Power (W)
Our design	92.62	1.5693	0.675
{$random}	92.56	1.5693	0.676
B. Fang et al. [29]	97.87	4.645	4.775
H. Fang et al. [30]	99.2	4.708 (125 MHz)	4.5

A significant limitation of many FPGA-based SNN accelerators is the absence of a spiking encoding module, necessitating encoding processing during pre-processing, typically handled by the CPU. Integrating the encoding directly into the FPGA can mitigate this bottleneck. The pre-processing tasks encompass image reading, image-to-spike train encoding, and serial file read/write operations. Upon the introduction of the encoding module to the FPGA system, the CPU's pre-processing time is notably reduced by more than threefold, decreasing from 405 s to 120 s.

3.2 Test for Poisson encoding with the same spike

Given that Poisson encoding represents a form of rate encoding, the spike trains generated at each timestep are time-independent. Therefore, it is plausible to utilize the same spike train for each timestep. Upon the arrival of the initial batch of images, the system encodes them into spike trains and stores the corresponding addresses in RAM. Subsequently, these addresses are read again in the subsequent timesteps, optimizing efficiency in spike train handling.

Analyzing the data in Table 4, it is evident that employing the same spike train for each timestep leads to a 1.69% reduction in accuracy. However, it significantly decreases the testing time on the FPGA by five times. This approach might be a viable consideration for applications prioritizing real-time processing over absolute accuracy, such as video surveillance.

Table 4 The impact of using the same Poisson encoding on accuracy and processing time.

Poisson encoding	Accuracy on CPU (%)	Time on CPU (s)	Accuracy on FPGA (%)	Time on FPGA (s)
Different	92.69	3.2214	92.62	1.5693
Same	90.19	1.5000	90.79	0.2916

3.3 Resource usage

The model is deployed on the Xilinx ZCU 102, and we conduct a comparison with two other implementations sharing a similar network architecture without the spiking encoding module. The resource usage comparison is presented in Table 5.

Table 5 System resource usage comparations.

	LUT	Register (FF)	BRAM	Time (s) (10,000 images)	Power (W)
This work	4342	620	5	1.5693	0.675
Shen et al. [31]	20,738	6549	100	3.522	1.584
Gupta et al. [32]	56,230	23,238	16	5	—

In Table 5, it is evident that the SNN system designed in this paper utilizes a minimal number of resources, showcasing efficient resource utilization. In comparison with the other two preceding works, our SNN system demonstrates reduced resource usage with 4342 look-up tables (LUTs), 620 flip-flops (FFs), and 5 block RAMs (BRAMs). Additionally, the total power dissipation is 0.675 W, reflecting lower power consumption. Moreover, our system is 2–3 times faster than the other two accelerators when inferring 10,000 images.

3.4 Embedded application

Given that the system processes pixel inputs, it can be seamlessly integrated into real-time classification systems for effective classification and detection. In this section, we specifically apply it to recognize digital numbers, as illustrated in Fig. 8.

Figure 8 Digital numbers recognition system.

The system workflow is illustrated in Fig. 9. Initially, the camera captures the image and transfers RGB pixels to the ZCU 102. Subsequently, the ZCU 102 resizes the image to 28×28 and converts the RGB pixel to a grayscale value. Finally, the SNN system reads the grayscale value, predicts it, and displays the result using LEDs

Figure 9 Digital numbers recognition system workflow.

4 Conclusion

In this paper, we introduce a novel implementation approach for an FPGA-based SNN accelerator with Poisson encoding. Leveraging LIF neurons, our design attains a classification accuracy of 92.62% for the MNIST dataset, concurrently reducing CPU pre-processing time by threefold and being 14× faster than CPU, 2.5× faster than GPU. The system operates at a power consumption of 0.675 W, showcasing efficiency in resource utilization compared to prior designs. Given its pixel-based input, this accelerator seamlessly integrates into real-time classification systems, facilitating efficient classification and detection.

Acknowledgments

Acknowledgements

This work was supported in part by the National Natural Science Foundation of China (Nos. 62104176 and 62171347), in part by the Fundamental Research Funds for the Central Universities (No. XJSJ23083), in part by the Proof of Concept Foundation of Xidian University Hangzhou Institute of Technology (No. GNYZ2023XJ0409-1), in part by the Shaanxi Higher Education Teaching Reform Research Project (No. 23ZZ014), and in part by the China Postdoctoral Science Foundation (No. 2019M663637).

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